1. Field of the Invention
The present invention relates to a circuit for generating internal power supply voltage in a semiconductor memory device.
2. Description of the Background Art
As semiconductor devices are miniaturized, there arises a need to decrease power supply voltage in order to ensure reliability of devices such as transistors. Although a static random access memory (SRAM) has a long life, external supply voltage would remain at 5.0V for sometime in the future. A circuit is required for generating internal supply voltage by decreasing the external supply voltage of 5.0 V. In the SRAM, especially of low power consumption type, the current consumed by the circuit for generating internal supply voltage increases, causing another problem. Accordingly, an internal supply voltage generating circuit which consumes less current or no current has been proposed.
FIG. 30 is a circuit diagram showing a structure of a conventional internal supply voltage generating circuit (voltage down converter) for an SRAM. As shown in FIG. 30, the internal supply voltage generating circuit is constituted by an N channel MOS transistor NT1 having its source, drain, and gate respectively connected to an internal supply node 31, an external supply node 30, and drain.
FIG. 31 shows an operation of the conventional internal supply voltage generating circuit shown in FIG. 30. When external supply voltage Vcc is supplied to external supply node 30, voltage as shown by the line 32 is generated on internal supply node 31 if the supplied voltage is not decreased. Voltage which is actually generated is equal to Vcc-Vth (NMOS) which is smaller than Vcc by threshold voltage Vth (NMOS) of the N channel MOS transistor NT1 as shown by the broken line.
It is noted that the threshold voltage Vth (NMOS) is increased since backgate voltage (potential difference between backgate and source) is increased by the increase of voltage from 0 V on the source of N channel MOS transistor NT1.
According to the current process for SRAM of 5 V supply voltage normally utilized, threshold voltage Vth (NMOS) is 0.7 V when the backgate voltage is 0 V. When voltage of 5.0 V is supplied to external supply node 30 of N channel MOS transistor NT1 shown in FIG. 30, voltage on internal supply node 31 is around 3.5 V. In this case, backgate voltage is -3.5 V and threshold voltage Vth (NMOS) is about 1.5 V.
In the internal supply voltage generating circuit shown in FIG. 30, an amount of decrease in voltage is determined as about 1.5 V. The voltage of 3.5 V obtained by decreasing 5 V by 1.5 V is still too high in the latest wafer process since the miniaturization is highly developed. Although it is possible to increase the amount of decrease in voltage by increasing threshold voltage Vth (NMOS), uniformly increased threshold voltage Vth (NMOS) of N channel NMOS transistors in a chip deteriorates the performance of the device. Further, additional process is needed in order to increase threshold voltage Vth (NMOS) of the N channel MOS transistor used for decreasing voltage, adding cost.